Design for testability of on-line multipliers
نویسندگان
چکیده
This paper deals with the test of an integrated on-line multiplier suitable for very large numbers. Due to the serial structure of the circuit, the controlability and observability of the different elements are very low. In particular, an embedded sequential Iterative Logic Array cannot be accessed directly and has no primary outputs. Thus some modifications of the circuit are made to enhance the controlability and the observability. Two DFT alternatives are presented here. The first determines what are the most significant nodes of the circuit to consider in order to avoid error masking. These nodes are observed by means of parity trees. The second approach increases the parallelism of the circuit and presents, thus, the advantage of a large reduction in the test duration. In addition, both options have a low area overhead and a reduced number of extra pins.
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Analytic approach for error masking elimination in on-line multipliers
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